A number of configurations in computer memory exist to protect data against errors or failure of memory devices. Detection/correction schemes, such as the Chipkill™ memory architecture, exist to protect computer memory systems from single memory chip failure as well as multi-bit errors from any portion of a single memory chip. In the Chipkill™ architecture, bits of multiple words of error correcting code data are scattered across multiple memory chips, such that the failure of any one memory chip will affect each value of the error correcting code data resembling multiple correctable errors. This configuration allows memory contents to be reconstructed despite the complete failure of one chip.
In computer hard drive memory, redundant arrays of inexpensive disks (RAID) configurations allow backup of data when multiple drives are configured in parallel, where n+1 drives are used to store data. The extra memory of the “1” drive of n+1 in a RAID 4 or RAID 5 configuration is used to store the error correcting code data. However, RAID configurations are often relatively slow to implement write operations because each write requires updating the error correcting code data, such that two writes are required for every operation (one for the data being written, and another for the updated error correcting code data being written). Thus, performance of a RAID 5 configuration when writing is approximately one half the reading performance. RAID data recovery operations can even be slower than half the speed of read operations, because all disks must be read individually to perform error recovery.